Some projects withheld for commercial or public identification reasons. The following is a dependency diagram for the projects listed.
Automated framework for massively parallel Monte Carlo testing of Icarus Verilog modules
RISC-V core written in Verilog to be synthesized on a Xilinx Spartan-7 FPGA
Project page (links currently dead)
Open-source, cooperative-multitasking operating system firmware for the Flipper Zero, written in Rust
Not yet public on Github
Open-source, highly portable, async-first networking stack written in C
Not yet public on Github
Reference implementation of a router with a fully open-source PCB and software written using TinyNeT